1. Field of the Invention
The present invention relates generally to signal processing circuits and methods, and more particularly to a signal processing circuit for processing a digital signal generated from a frequency modulation (FM) signal in an optical disk apparatus and a method of processing such a digital signal.
2. Description of the Related Art
Conventionally, a signal processing circuit used for generating a digital FM signal from an FM signal is provided in a reproduction system of an optical disk apparatus.
FIG. 1 is a block diagram showing a conventional signal processing circuit 10, and FIG. 2 is an ideal timing chart of signals in the conventional signal processing circuit 10. In FIG. 1, the signal processing circuit 10 includes a two-edge detection circuit 11, a counter circuit 12, a latch circuit 13, and a digital low-pass filter (LPF) circuit.
The two-edge detection circuit 11 is supplied with an FM signal shown in FIG. 2(a) from a terminal 15. The two-edge detection circuit 11 converts the supplied FM signal into an FM pulse signal shown in FIG. 2(b) so that a level of the FM pulse signal becomes “High” when a level of the FM signal is higher than a zero level and “Low” when the level of the FM signal is lower than the zero level. Further, the two-edge detection circuit 11 generates a two-edge signal 18 shown in FIG. 2(c) by detecting rising and falling edges of the FM pulse signal. The two-edge signal 18 is supplied to the counter circuit 12, the latch circuit 13 and the digital LPF circuit 14.
The counter circuit 12 is supplied with clock pulses from a terminal 16 and with the two-edge signal 18 from the two-edge detection circuit 11. The counter circuit 12 counts the clock pulses to supply a counted value 19 expressed in bits Q1 through Qn to the latch circuit 13. Also, as receiving the two-edge signal 18, the counter 12 is reset by the two-edge signal 18 and counts the clock pulses between the rising and falling edges.
In FIG. 2(d), when the count of the clock pulses is continued until the counted value reaches N1, the counted value is reset by an edge output of the two-edge signal 18 shown in FIG. 7(c) to become zero. After the counter circuit 12 is reset, the count of the clock pulses is resumed. When the count continues until the counted value reaches N2, the counted value is again reset by an edge output of the two-edge signal 18. Thus, the counted value becomes N1, N2, N3, and N4 in the order listed each time the counter circuit 12 is reset by the two-edge signal 18.
The latch circuit 13 is supplied with the counted value 19 from the counter circuit 12 and with the two-edge signal 18 from the two-edge detection circuit 11. The latch circuit 13 latches the counted value 19 based on timings of edge outputs of the two-edge signal 18. In FIG. 2(d), the latch circuit 13 latches each of the counted values N1 through N4 at each timing at which the counted value is reset. A latched counted value 20 is supplied to the digital LPF 14.
The digital LPF 14 is supplied with the latched counted value 20 from the latch circuit 13 and with the two-edge signal 18 from the two-edge detection circuit 11. The digital LPF 14 performs a digital processing on the FM signal based on the latched counted value 20 supplied from the latch circuit 13 so as to eliminate high frequency components from the FM signal. The digitally processed FM signal is supplied to a terminal 17. A signal processing is then performed based on an output digital data of the digital LPF 14.
Thus, according to the signal processing circuit 10, the two-edge signal 18 generated from the FM pulse signal generated from the FM signal is detected, so that the counter circuit 12 counts the number of the clock pulses based on timings of edge outputs of the two-edge signal 18. The digital processing is then performed based on the counted value of the clock pulses and the signal processing is further performed.
In the case of performing the signal processing at the ideal timings shown in FIG. 2, a signal or a counted value based on the FM signal can be obtained, and therefore a correct digital FM signal can be obtained. However, an actual FM signal contains noises.
FIG. 3 is a diagram showing a waveform of an actual FM signal and an enlarged view of the waveform around a zero level. In FIG. 3, since the FM signal crosses the zero level a plurality of times in its neighborhood due to noises contained in the FM signal, each of rising and falling edges of the FM signal is detected a plurality of times. Therefore, the two-edge detection circuit 11 shown in FIG. 1 is prevented from correctly detecting the rising and falling edges of the FM signal, thus preventing a correct two-edge signal 18 from being supplied.
FIG. 4 is a timing chart in an actual signal processing. FIGS. 4(a) through (d) show an FM pulse signal, a two-edge signal, clock pulses (CLK), and a count value, respectively. A timing chart of each signal of FIG. 4 is based on the actual FM signal shown in FIG. 3, which signal contains the noises.
Since the FM signal shown in FIG. 3 crosses the zero level a plurality of times due to the noises contained in the FM signal, the FM pulse signal shown in FIG. 4(a) includes a plurality of risings and failings in respective rising and falling periods T1 and T2 of the FM pulse signal. These risings and failings are called chattering.
Due to the chattering generated in the FM pulse signal, a plurality of edges are detected in the respective periods T1 and T2 as shown in FIG. 9(b). Therefore, a position at which the count of the clock pulses is started cannot be determined correctly, thus preventing the counted value shown in FIG. 4(d) from being correctly obtained.
Accordingly, in the case of processing the actual FM signal in the signal processing circuit, a signal processing is prevented from being performed on a correct digital FM signal due to the chattering caused in the FM pulse signal by the noises contained in the FM signal.
For this reason, a below-described method has been employed so that a correct digital FM signal can be obtained even in the case of processing the FM pulse signal in which the chattering is caused.
FIG. 5 is a timing chart of signals in a conventional method of eliminating chattering. FIGS. 5(a) through (c) show an FM pulse signal, an FM pulse signal from which the chattering is eliminated, and a two-edge signal, respectively. After the chattering is eliminated from the FM pulse signal of FIG. 5(a) in the two-edge detection circuit 11 shown in FIG. 1, the FM pulse signal of FIG. 5(a) is converted into the FM pulse signal of FIG. 5(b). The two-edge signal of FIG. 5(c) is generated based on the FM pulse signal of FIG. 5(b).
With respect to the chattering-eliminated FM pulse signal of FIG. 5(b), if chattering is caused at a timing t1, for example, a rising edge is prevented from being confirmed until a timing t2 at which the chattering disappears. Then, after the FM pulse signal is maintained at a constant level for a predetermined period T3, the FM pulse signal confirms the detection of the rising edge at a timing t3. At this time, a period Tx is required for confirming the detection of the rising edge of the chattering-eliminated FM pulse signal.
Next, if chattering is caused at a timing t4, a falling edge is prevented from being confirmed until a timing t5 at which the chattering disappears. Then, after the FM pulse signal is maintained at a constant level for the predetermined period T3, the FM pulse signal confirms the detection of the falling edge at a timing t6. At this time, a period Ty is required for confirming the detection of the falling edge of the chattering-eliminated FM pulse signal.
On the other hand, since no chattering is caused at timings t7 and t9, the respective detections of rising and falling edges are delayed by the predetermined period T3 so as to be confirmed at timings t8 and t10, respectively.
Thus, the chartering-eliminated FM pulse signal is generated by such a method which confirms the detection of a rising or falling edge when the FM pulse signal is maintained at a constant level for a predetermined period. In this method, when chartering is caused, a delay in confirming the detection of an edge is a total of a period required before the disappearance of the chattering and the predetermined period, and when no chattering is caused, the delay is only the predetermined period.
As previously described, an actual signal contains noises, thus preventing a rising or falling edge of the signal from being detected at a constant period. Therefore, a correct signal processing is prevented from being performed.
Further, in the case of confirming the detection of an edge by delaying the confirmation, in order to eliminate the noises, for a total of a predetermined period and a period during which the noises are caused, a delay in detecting the edge differs depending on the presence or absence of the noises. Therefore, a period of the signal is changed. Thereby, the counted value becomes abnormal and a value held by the latch circuit is also increased/decreased with respect to a normal value. As a result, a correct signal cannot be obtained.